Title :
800 megabyte per second systems via use of synchronous DRAM
Author_Institution :
Texas Instrum. Inc., Stafford, TX, USA
Abstract :
DRAMs, as we know them today, do not satisfy the bandwidth needs of the processor. With today´s architecture, the interface would have to grow in width, becoming so large as to be unmanageable. The memory bandwidth bottleneck has several solutions. The most economical solution is the SDRAM, meeting the challenge in the near future for the 100 to 200 MHz needs, and a path to the needs beyond the year 2000.<>
Keywords :
DRAM chips; memory architecture; technological forecasting; 100 to 200 MHz; 800 MByte/s; SDRAM; future; interface; memory architecture; memory bandwidth; synchronous DRAM; Bandwidth; Costs; Instruments; Interleaved codes; Microprocessors; Random access memory; Reflection; Registers; SDRAM; Traffic control;
Conference_Titel :
Compcon Spring '94, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-5380-9
DOI :
10.1109/CMPCON.1994.282914
