DocumentCode :
1719177
Title :
Test chip and data considerations for MOS parameter extraction
Author :
Karlsson, Peter R. ; Jeppson, Kjell O.
Author_Institution :
Dept. of Solid State Electron., Chalmers Univ. of Technol., Goteborg, Sweden
fYear :
1997
Firstpage :
159
Lastpage :
164
Abstract :
This paper presents an investigation of principles for test chip design and data point selection for MOS parameter extraction methods using a low number of data points. Variations in extracted parameter values for different combinations and numbers of data points are studied experimentally. The influences on the standard deviations of VT , β, θ, RS, ΔW and ΔL of different data point selections and device combinations are studied using synthetic data with multiplicative noise
Keywords :
MOS integrated circuits; characteristics measurement; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; integrated circuit testing; parameter estimation; MOS parameter extraction; data point selection; device combinations; multiplicative noise; standard deviations; test chip design; Chip scale packaging; Circuit noise; Data mining; Electronic equipment testing; Geometry; MOSFETs; Noise measurement; Parameter extraction; Semiconductor device measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
Type :
conf
DOI :
10.1109/ICMTS.1997.589375
Filename :
589375
Link To Document :
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