Design rules for diode-clamped multilevel inverters used in medium-voltage applications

In medium voltage applications, diode-clamped multilevel inverters (DCML) are often used to eliminate bulky transformers and thus, they are coupled directly to the grid. As a consequence, the DC-link voltages are several times higher than the nominal semiconductor device voltages. This leads to an additional degree of freedom in the design of the converters: the number of levels and the number of semiconductor devices per level. The objective of this paper is to determine design rules for diode-clamped multilevel converters, which gives the optimum number of levels in consideration of additional power circuitries, which have to be installed to balance the tapped DC-bus capacitors.