Design of SDRAM Controller in High-Speed Data Acquisition Based on PCI Bus

To solve the problem of large capacity and high speed storage requirement in PCI high-speed data acquisition system (HDAS), a scheme of utilizing FPGA to realize the timing-logical control for the synchronous DRAM (SDRAM), which is used as a data memory, is proposed. After analyzing the structural features of the SDRAM, the idea of design for SDRAM controller with Verilog HDL is given in detail. In the mean time, the FIFO technique is especially employed to solve the problem that SDRAM accessed by computer through PCI bus. Lastly, the correctness of the design is proved by the corresponding timing simulation.