The VCU SRC II: a full-custom VLSI 32-bit RISC processor

Author

Kim, Austin ; Weistroffer, George R. ; Grammer, David M. ; Klenke, Robert H.

Author_Institution

Dept. of Electr. Eng., Virginia Commonwealth Univ., Richmond, VA, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

201

Lastpage

204

Abstract

Heuring and Jordan define a simplified, 32-bit RISC processor instruction set architecture called the simple RISC computer. An extended form of this architecture is defined, a gate-level logic design is developed, and a full-custom VLSI implementation is laid out in a 0.5 μm CMOS process, fabricated, and tested. The processor design flow, from ISA definition to IC testing, is carried out by junior- and senior-level undergraduate engineering students over two consecutive semesters as part of an integrated curriculum

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; electronic engineering education; integrated circuit design; integrated circuit testing; logic design; logic testing; microprocessor chips; reduced instruction set computing; student experiments; 0.5 micron; 32 bit; CMOS process; IC fabrication; IC testing; RISC processor instruction set architecture; VCU SRC II custom VLSI RISC processor; custom VLSI implementation; gate-level logic design; integrated curriculum; processor design flow; simple RISC computer; undergraduate engineering students; CMOS process; Computer aided instruction; Computer architecture; Instruction sets; Integrated circuit testing; Logic design; Logic testing; Process design; Reduced instruction set computing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 2001. Proceedings of the Fourteenth Biennial

Conference_Location

Richmond, VA

ISSN

0749-6877

Print_ISBN

0-7803-6691-3

Type

conf

DOI

10.1109/UGIM.2001.960330

Filename

960330