DocumentCode
1721842
Title
Design of digitally assisted 1.5b/stage pipeline ADCs using fully differential current conveyors
Author
Balasubramaniam, Harish ; Hofmann, Klaus
Author_Institution
Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
fYear
2011
Firstpage
873
Lastpage
876
Abstract
This paper introduces 1.5b/stage pipeline ADCs based on a fully differential current conveyor (CC). A comparison between the traditional MDAC architecture and the passive common mode suppressed MDAC as well as a new foreground calibration technique to correct the ADC errors is presented. The ADCs implemented in 90nm work at 10MHz sampling rate for input voltages of (-500mV, 500mV) and provide varying resolutions of 8 and 10 bits.
Keywords
analogue-digital conversion; calibration; current conveyors; foreground calibration; frequency 10 MHz; fully differential current conveyors; passive common mode; pipeline analog-digital convertors; size 90 nm; voltage -500 mV; voltage 500 mV; CMOS integrated circuits; Calibration; Capacitors; Equations; Noise; Pipelines; Registers; Current Conveyor; Foreground Calibration; Fully Differential CCII; Pipeline ADC;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design (ECCTD), 2011 20th European Conference on
Conference_Location
Linkoping
Print_ISBN
978-1-4577-0617-2
Electronic_ISBN
978-1-4577-0616-5
Type
conf
DOI
10.1109/ECCTD.2011.6043819
Filename
6043819
Link To Document