An improved BCD adder using 6-LUT FPGAs

The need for high performance decimal arithmetic is required in many applications. Using binary system to process decimal numbers tends to be costly in terms of area and speed. Hence, there is a demand to realize decimal operations efficiently. In this paper, an improved approach to implement decimal addition is proposed. A hardware implementation of this arithmetic function is developed based on 6-input LUTs and the fast carry chains. In our proposed approach, a new architecture of a BCD adder is presented with emphasis on critical path delay reduction. The adder architecture has been implemented on Xilinx Virtex-6 FPGA for operand sizes from 2 to 18 digits. Our design has outperformed other approaches in terms of area and delay. On average, the delay reduction is 13.1% and LUT saving is 28.9% compared to a conventional BCD adder.