FPGA implementation of rate-compatible QC-LDPC code decoder

The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as simplified code representations in the encoder and decoder. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. The decoder uses check node merging to increase the convergence speed of the algorithm. Check node merging allows the decoder to achieve the same performance with a significantly lower number of iterations, thereby increasing the throughput. The feasibility of a check node merging decoder is investigated for codes from IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the check node merging algorithm allows the decoder to be implemented using lower parallelization factors, thereby reducing the logic complexity. The designs have been synthesized to an Altera Cyclone II FPGA, and results show significant increases in throughput at high SNR.