مرکز منطقه ای اطلاع رساني علوم و فناوري - "A sub-0.25μm symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering"

DocumentCode :

1722492

Title :

"A sub-0.25μm symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering"

Author :

Wada, Shigeki ; Tokushima, Masatoshi ; Fukaishi, Muneo ; Matsuno, Noriaki ; Yano, Hitoshi ; Hida, Hikaru

Author_Institution :

NEC Corporation

fYear :

1994

fDate :

6/16/1905 12:00:00 AM

Firstpage :

145

Lastpage :

146

Keywords :

Capacitance; Collimators; Electrodes; Filling; Gold; Lithography; Roentgenium; Sputtering; Substrates; Threshold voltage;

fLanguage :

English

Publisher :

ieee

Conference_Titel :

Device Research Conference, 1994. 52nd Annual

Type :

conf

DOI :

10.1109/DRC.1994.1009449

Filename :

1009449

Link To Document :

https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1722492