Title :
Gain reduction by gate-leakage currents in regulated cascodes
Author :
Schlögl, F. ; Schneider-Hornstein, K. ; Zimmermann, H.
Author_Institution :
Inst. of Electr. Meas. & Circuit Design, Vienna Univ. of Technol., Vienna
Abstract :
The gain reduction of nanometer-size MOS transistors due to the high output conductance of the devices is already discussed in the literature. This paper discusses an additional issue which leads to further gain reduction - the gate-leakage current. On the basis of the example of a regulated cascode in 130 nm CMOS and in 65 nm CMOS it is estimated that this shrinking step decreases the gain due to gate-leakage current by about 30 to 40 dB.
Keywords :
CMOS integrated circuits; MOSFET; leakage currents; CMOS; cascode; gain reduction; gate-leakage current; nanometer-size MOS transistor; size 130 nm; size 65 nm; Circuit synthesis; Energy consumption; Gate leakage; Leakage current; MOSFETs; Parasitic capacitance; Signal design; Transconductance; Transistors; Voltage;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538755
