Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs

A concurrent error detection (CED) scheme for combinational logic blocks implemented with embedded memory blocks (EMBs) available in today´s FPGAs is proposed. The scheme guarantees the detection of each permanent or transient fault resulting in a single-bit error at the input or output of any component of the circuit. Extensions of the basic scheme aimed at increasing the set of target faults are also presented. For the examined benchmark circuits, an average overhead associated with the proposed CED scheme is 24.7%, whereas for the earlier presented CED techniques applicable to conventional gate-based designs, an average overhead for the same circuits is in the range of 60%. The proposed technique offers also lower speed degradation and lower extra power consumption than the techniques intended for conventional gate-based designs.