Title :
A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units
Author :
Petcu, Virgil E. ; Amaricai, Alexandru ; Vladutiu, Mircea
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. Politeh. of Timisoara, Timisoara
Abstract :
This paper presents a new type of coprocessor architecture suited for both conventional floating point and interval arithmetic. The coprocessor is composed of two logical processors (LP). The floating point units are shared between these two LPs in order to reduce the area overhead. Some functional units implement two or more operations (for example the multiply-add fused (MAF) unit can be used for addition, multiplication or multiply-add fused). The set of functional units can thus help reduce the number of structural hazards and increase the resource utilization (for example, if addition occurs on both LPs, one can be executed on the adder, while the other on the MAF). In order to further reduce the data and structural hazards a scheduler for this architecture is also proposed.
Keywords :
coprocessors; floating point arithmetic; coprocessor architecture; dual-threaded architecture; floating point arithmetic; interval arithmetic coprocessor; logical processors; multiply-add fused unit; shared floating point units; structural hazards; Clocks; Computer architecture; Coprocessors; Floating-point arithmetic; Hazards; Pipelines; Reduced instruction set computing; Resource management; Scheduling; Yarn; Simultaneous multi-threading; interval arithmetic; parallel architectures;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538774
