DocumentCode :
1723431
Title :
RC-Cache: Soft error mitigation techniques for low-leakage on-chip caches
Author :
Sun, Yan ; Zhang, Minxuan ; Li, Shaoqing ; Song, Chao ; Zhao, Yali
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Volume :
3
fYear :
2010
Abstract :
This paper presents a kind of reliable low-leakage cache - RC-Cache, to solve the problem of high soft error rate in low-leakage on-chip caches. The proposed structure combines circuit technique and micro-architecture technique, and can reduce impacts of soft errors on leakage power optimization technique of caches. At circuit level, we improve the soft error immune of SRAM through specially designed soft error immune SRAM cell - SI-SRAM; at microarchitecture level, we reduce the soft error vulnerability of low-leakage caches by burst-based access prediction and early write-back operation. Experimental results show that in normal mode, soft error rate of RC-Cache is only 1/7 of the conventional cache, and in drowsy mode it is just 2/5. The techniques significantly improve the reliability of caches and, to a certain extent, mitigate soft error problem of low-leakage on-chip caches.
Keywords :
SRAM chips; cache storage; circuit analysis computing; fault diagnosis; leakage currents; memory architecture; power aware computing; RC-cache; SRAM cell; burst-based access prediction; circuit technique; leakage power optimization; low-leakage cache; microarchitecture technique; soft error mitigation technique; write-back operation; Computer architecture; Error analysis; Logic gates; Microprocessors; Random access memory; Reliability; Transistors; SRAM; drowsy cache; leakage; low-power; reliability; soft error;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (ICSPS), 2010 2nd International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-1-4244-6892-8
Electronic_ISBN :
978-1-4244-6893-5
Type :
conf
DOI :
10.1109/ICSPS.2010.5555852
Filename :
5555852
Link To Document :
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