• DocumentCode
    1723480
  • Title

    Design of Time-to-Digital Converter Output Interface

  • Author

    Miskowicz, Marek

  • Author_Institution
    Dept. of Electron., AGH Univ. of Sci. & Technol., Cracow
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A design of time-to-digital converter output interface for ADCs with asynchronous sigma-delta modulation is presented in details in the paper. The concept of the digital interface with double data buffering and asynchronous serial link is carefully explained on the basis of the schematics of particular functional blocks. The TDC design has been optimized in terms of minimizing the power consumption.
  • Keywords
    low-power electronics; sigma-delta modulation; analogue-digital converter; asynchronous serial link; asynchronous sigma-delta modulation; data buffering; functional blocks; power consumption; time-to-digital converter output interface design; Buffer storage; Clocks; Computer buffers; Counting circuits; Delta-sigma modulation; Design optimization; Flip-flops; Quantization; Sampling methods; Variable speed drives;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
  • Conference_Location
    Bratislava
  • Print_ISBN
    978-1-4244-2276-0
  • Electronic_ISBN
    978-1-4244-2277-7
  • Type

    conf

  • DOI
    10.1109/DDECS.2008.4538775
  • Filename
    4538775
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1723480