DocumentCode :
1723512
Title :
An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture
Author :
Forbes, Shanna-Shaye ; Patel, Hiren D. ; Lee, Edward A. ; Andrade, Hugo A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA
fYear :
2008
Firstpage :
322
Lastpage :
325
Abstract :
Most common real-time embedded programming languages provide a means to specify functionality; however, they have few constructs to specify precise timing constraints. LabVIEW is one example of a graphical programming language that supports timing specifications in the form of timed-loops. In this work, we present a plug-in for LabVIEW Embedded that maps the LabVIEW G graphical programming language and its timing specifications to the PREcision Timed machine (PRET), an architecture that exposes timing instructions in its instruction set architecture. We demonstrate the use of the plug-in with a simple producer/consumer example that uses timing to enforce synchronization.
Keywords :
embedded systems; visual languages; LabVIEW G; graphical programming language; precision timed architecture; real-time embedded programming languages; timed functional specification; Computer architecture; Computer languages; Embedded system; Instruction sets; Jitter; Microprocessors; Operating systems; Real time systems; Registers; Timing; Programming Model; Real-Time Embedded Systems; Timing Predictability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Distributed Simulation and Real-Time Applications, 2008. DS-RT 2008. 12th IEEE/ACM International Symposium on
Conference_Location :
Vancouver, BC
ISSN :
1550-6525
Print_ISBN :
978-0-7695-3425-1
Type :
conf
DOI :
10.1109/DS-RT.2008.45
Filename :
4700137
Link To Document :
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