Title :
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
Author_Institution :
Dept. of Signal Process., UTIA, Prague
Abstract :
This paper analyses applicability of partial runtime reconfiguration (PRR) in fault emulators based on FPGAs of Xilinx Virtex family. PRR is used for loading emulator modules and for injecting faults into the emulated circuit. Since the time of reconfiguration may have significant impact on its usability, this paper deals with this issue. The goal was to accelerate PRR and to evaluate the time needed for fault injection by PRR on these FPGAs. Experimental results show that we have achieved up to eight times faster reconfiguration compared to the original Xilinx method, and fault injection time about 77 mus per one emulated fault.
Keywords :
fault diagnosis; fault simulation; field programmable gate arrays; Xilinx FPGAs; Xilinx Virtex family; fault emulator; fault injection; loading emulator modules; partial runtime reconfiguration; Acceleration; Circuit faults; Emulation; Field programmable gate arrays; Flip-flops; Lasers and Electro-Optics Society; Reconfigurable logic; Runtime; Table lookup; Usability;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538781
