Title :
Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits
Author :
Rozkovec, Martin
Author_Institution :
Inst. of Inf. Technol. & Electron., Tech. Univ. in Liberec, Liberec
Abstract :
This paper presents the BIST architecture for SoPC circuits. DyRespin reuses scan chains in embedded cores for decompression of highly compressed test vectors. The test access mechanism (TAM) for scan chain connections is implemented as a reconfigurable module. We reuse the switching logic in the interconnection matrix in order to save logic resources. For circuits with higher number of scan chains, the reconfigurable TAM is much more effective than the multiplexer based TAM, comparing usage of the logic resources and clock speeds.
Keywords :
built-in self test; embedded systems; field programmable gate arrays; system-on-chip; BIST architecture; FPGA circuits; SoPC circuits; built-in self test; clock speeds; dynamically reconfigurable test architecture; embedded systems; highly compressed test vectors; interconnection matrix; logic resources; reconfigurable module; scan chain connections; switching logic; system on a programable chip; test access mechanism; Built-in self-test; Circuit testing; Electronic equipment testing; Field programmable gate arrays; Flexible printed circuits; Integrated circuit interconnections; Logic devices; Modems; Multiplexing; Reconfigurable logic;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538782
