DocumentCode :
1723688
Title :
A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator
Author :
Okuno, Keisuke ; Konishi, Toshihiro ; Izumi, Shintaro ; Yoshimoto, Masahiko ; Kawaguchi, Hiroshi
Author_Institution :
Kobe Univ., Kobe, Japan
fYear :
2012
Firstpage :
289
Lastpage :
292
Abstract :
This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) and a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop´s metastability to the next GRO, and thus improves its linearity over the conventional masters-lave d-type flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s.
Keywords :
CMOS logic circuits; circuit stability; flip-flops; integrated circuit noise; linearisation techniques; logic gates; oscillators; quantisation (signal); time-digital conversion; GRO; NOR gate; SNDR; linearity improvement; metastability; quantization noise propagator; second-order gated ring oscillator TDC; second-order noise shaping time-to-digital converter; size 65 nm; standard CMOS process; two-stage DDFF; two-stage dynamic d-type flipflops; Clocks; Delay; Logic gates; Noise; Noise shaping; Quantization; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0857-1
Electronic_ISBN :
978-1-4673-0858-8
Type :
conf
DOI :
10.1109/NEWCAS.2012.6329013
Filename :
6329013
Link To Document :
بازگشت