DocumentCode :
1723716
Title :
Efficient Allocation of Verification Resources using Revision History Information
Author :
Nacif, José Augusto ; Silva, Thiago ; Tavares, A.I. ; Fernandes, Antônio O. ; Coelho, Claudionor N., Jr.
Author_Institution :
Comput. Sci. Dept., Univ. Fed. de Minas Gerais, Belo Horizonte
fYear :
2008
Firstpage :
1
Lastpage :
5
Abstract :
Verifying large industrial designs is getting harder each day. The current verification methodologies are not able to guarantee bug free designs. Some recurrent questions during a design verification are: Which modules are most likely to contain undetected bugs? In which modules the verification team should concentrate their effort? This information is very useful, because it is better to start verifying the most bug-prone modules. In this work we present a novel approach to answer these questions. In order to identify these bug-prone modules, the revision history of the design is used. Using information of an academic experiment, we demonstrate that there is a close relationship between bugs/changes history and future bugs. Our results show that allocating modules for verification based on bugs/changes leaded to the coverage of 91.67% of future bugs, while random based strategy covered only 37.5% of the future bugs.
Keywords :
program debugging; program verification; bug-prone modules; revision history information; verification resources; Computer bugs; Computer industry; Computer science; Design automation; Hardware; History; Predictive models; Process design; Resource management; Software engineering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
Type :
conf
DOI :
10.1109/DDECS.2008.4538784
Filename :
4538784
Link To Document :
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