IP-based Systematic Design of Power-and Matching-limited Circuits

Author

Smola, David ; Pantucek, Ludek

Author_Institution

AMI Semicond. Czech, s.r.o., Brno

fYear

2008

Firstpage

1

Lastpage

6

Abstract

In this paper we present a systematic top-down methodology for designing power-limited and matching-limited circuits with a help of IP database. The presented methodology is a helpful tool for the circuit performance optimization and for the design time shortening. The approach is illustrated on a design of a measuring channel front-end, which senses an external high-voltage signal. The circuit is a signal conditioning front-end for an A/D converter input where the critical design parameters are the power consumption, the matching and the transient response and last but not least the design time. The circuit was implemented in an ASIC and manufactured in 0.35 mum high-voltage CMOS technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; circuit optimisation; integrated circuit design; A/D converter; ASIC; IP database; IP-based systematic design; circuit design; circuit performance optimization; external high-voltage signal; high-voltage CMOS technology; matching-limited circuits; measuring channel front-end; power consumption; power-limited circuits; signal conditioning front-end; Application specific integrated circuits; CMOS technology; Circuit optimization; Databases; Design methodology; Design optimization; Energy consumption; Manufacturing; Signal design; Transient response;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on

Conference_Location

Bratislava

Print_ISBN

978-1-4244-2276-0

Electronic_ISBN

978-1-4244-2277-7

Type

conf

DOI

10.1109/DDECS.2008.4538790

Filename

4538790