A high performance CABAC encoder

One key technique for improving the coding efficiency of H.264 video standard is the entropy coder, context-adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is far higher than the table driven entropy encoding schemes such as the Huffman coding. CABAC is also bit serial and its multi-bit parallelization is extremely difficult. For a high definition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, the authors provided efficient solutions for the arithmetic coder and the renormalizer. An FPGA implementation of the proposed scheme capable of 54 Mbps encoding rate and test results are presented. A 0.18 μm ASIC synthesis and simulation shows 87 Mbps encoding rate utilizing an area of 0.42 mm².