Title :
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration
Author :
Starecek, Lukas ; Sekanina, Lukas ; Kotasek, Zdenek
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol., Brno
Abstract :
In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.
Keywords :
integrated circuit design; integrated circuit testing; network topology; circuit testing; circuit topology; gate-level reconfiguration; test vectors volume reduction; Automatic test pattern generation; Circuit faults; Circuit testing; Circuit topology; Combinational circuits; Energy consumption; Information technology; Logic functions; System testing; Test pattern generators;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-2276-0
Electronic_ISBN :
978-1-4244-2277-7
DOI :
10.1109/DDECS.2008.4538796
