Mapping multiplexers onto hard multipliers in FPGAs

Modern FPGAs now contain a selection of "hard" digital structures such as memory blocks and multipliers (Altera, 2003, Xilinx, 2003, QuickLogic, 2003, Actel, Lattice, 2004) in addition to the usual "soft" programmable logic typically consisting of lookup tables (LUTs) and flip-flops. These hard structures are a major benefit (in area and speed) for those applications that need them, but are completely wasted if an application circuit docs not require them. Finding other ways to use these structures will benefit these applications. In this paper, the authors presented a technique to map multiplexers to unused hard multipliers on an FPGA. An RTL synthesis tool flow that implements this technique over a set of benchmarks was created. While some circuits see no reduction in LUT count at all, others show meaningful improvements ranging from 10% to 70%. On average across the whole set of circuits the technique achieves a 7.3% reduction on the number of LUTs used. In some cases, however, the operating frequency of the circuit is reduced significantly.