Simulation of the response of external ESD protection circuits for CMOS ICs

CMOS ICs are highly susceptible to electrostatic discharge (ESD) induced voltage/current stresses. The IC manufacturer provides an on-chip protection circuit for improving the ESD susceptibility threshold of CMOS devices. However, device failures continue to occur due to electrical overstress (EOS) or due to ESD. For example, the CD4050B device has a built in immunity level of 2 kV for the human body model (HBM) ESD waveform. Hence the EOS/ESD failures noticed in these devices may be either due to a HBM-ESD stress level which is higher than 2 kV or due to other types of work practice/area related ESD stress waveform. Thus, there appears to be a need for providing external ESD protection circuits such that the device performance is not affected adversely. This paper gives an account of studies made using SPICE and MC4 circuit simulation software, to determine the effectiveness of some of the HBM-ESD external protection circuits