Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system

This work presents a dual mode, single carrier (SC) and high speed interface (HSI), wireless baseband receiver which implements the IEEE standards 802.15.3c [1] and 802.11.ad [2]. The proposed architecture of the baseband receive is designed as 8-parallelism with feed-forward data path reducing the operating frequency and can achieve high throughput for indoor communication. Besides, our goal is to demonstrate the system on Xilinx VC707 FPGA evaluation board and achieve multi-Gb/s data speed and low bit error rate (BER). The data rates achieved by the prototype are 1.5 Gb/s and 4.5 Gb/s for QPSK and 64QAM data in HSI mode, respectively. The specified (BER) of 10^-2 has been achieved for QPSK and 64QAM data at 8.3dB and 22.6dB, respectively.