SoCECT: System on Chip Embedded Core Test

This paper presents SoCECT (system on chip embedded core test), a novel test controller architecture that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. SoCECT makes use of the IEEE 1149.1 JTAG state machine to operate the test controller and also to allow for future integration with an IEEE P1687 interface. SoCECT also includes a test access mechanism (TAM) methodology(distributed architecture) that reuses the physical connections of the SoC system bus to provide an efficient transport medium for structural and functional test vectors between the embedded test controller and IEEE 1500 wrapped cores.