Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

Author

Yan Chen ; Yuan En Yu ; Yu Cheng Lin ; Chih Hung Hsieh ; Muh-Tian Shiue ; Chih-Feng Wu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chunli, Taiwan

fYear

2015

Firstpage

210

Lastpage

211

Abstract

In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm² with the power consumption of 89.9 mW at the supply voltage of 1.0 V.

Keywords

CMOS integrated circuits; carrier transmission on power lines; channel estimation; equalisers; fast Fourier transforms; quadrature amplitude modulation; radio receivers; synchronisation; 1024-QAM constellation; CMOS process; FFT; IEEE P1901 specification; PLC system; bit rate 170 Mbit/s; channel equalization; channel estimation; digital baseband inner receiver; digital received filter; fast Fourier transform; power 89.9 mW; power line communication system; size 90 nm; timing frequency offset synchronization; voltage 1.0 V; Baseband; Channel estimation; Layout; Least squares approximations; OFDM; Receivers; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics - Taiwan (ICCE-TW), 2015 IEEE International Conference on

Conference_Location

Taipei

Type

conf

DOI

10.1109/ICCE-TW.2015.7216860

Filename

7216860