Yield optimization for third party library elements

Optimization of semiconductor product yield requires control of systematic defects. A variety of industry tools are available to check designs for systematic layouts that will be difficult to manufacture. Because of the cost associated with setting up the rules for a checking tool and the cost of licenses needed to evaluate designs, manufacturing process lines typically enable a limited set of tools to evaluate designs for systematic yield sensitivity. Semiconductor product design systems typically incorporate library elements designed by third party design companies. When third party library suppliers do not have access to the licenses or expertise to use the tools selected by the target manufacturing line, a barrier is created to having all library elements in a semiconductor design system checked to the same level. This results in a yield exposure for library elements that are not evaluated and fixed. This paper describes a method used to enable systematic yield evaluation for 32nm library elements procured from third party library suppliers. The third party library supplier provides layout data to the contracting library owner for yield sensitivity analysis. Changes are prioritized and fed back to the third party library supplier. This method interlocks design practices with the third party library supplier and provides a means for the contracting library owner to evaluate third party library elements and provide feedback to optimize the design.