Title :
Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate Layer with Vfb controllability
Author :
Kakushima, K. ; Koyanagi, T. ; Kitayama, D. ; Kouda, M. ; Song, J. ; Kawanago, T. ; Mamatrishat, M. ; Tachi, K. ; Bera, M.K. ; Ahmet, P. ; Nohira, H. ; Tsutsui, K. ; Nishiyama, A. ; Sugii, N. ; Natori, K. ; Hattori, T. ; Yamada, K. ; Iwai, H.
Author_Institution :
Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (Vfb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the Vfb to positive direction.
Keywords :
MOS capacitors; MOSFET; cerium compounds; elemental semiconductors; high-k dielectric thin films; lanthanum compounds; leakage currents; permittivity; semiconductor-insulator boundaries; silicon; La2O3-CeO2; LaCe-silicate layer; Si; dielectric constant; equivalent oxide thickness; gate oxide scaling; leakage current; size 0.64 nm; Annealing; Atomic layer deposition; Dielectrics; High K dielectric materials; Logic gates; Metals; Silicon;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556115
