Title :
VLSI implementation of bit-parallel word-serial multiplier in GF(2233)
Author :
Tang, Wenkai ; Wu, Huapeng ; Ahmadi, Majid
Author_Institution :
Infineon Technol., Xi´´an, China
Abstract :
A bit-parallel word-serial (BPWS) finite field multiplier in GF(2233) is proposed in this paper. The complexities are lower than or comparable to those of the previous similar proposals. A VLSI implementation of the BPWS multiplier combined with a bit-parallel squarer is also presented. The fabricated ASIC chip can be used as the finite field arithmetic module on an elliptic curve technique based cryptographic accelerator board and the proposed VLSI design could also be utilized as a design IP core for fast implementation of a cryptographic processor or smart card.
Keywords :
Galois fields; VLSI; application specific integrated circuits; digital arithmetic; integrated circuit design; logic design; multiplying circuits; ASIC chip; Galois fields; VLSI design; VLSI implementation; bit-parallel squarer; bit-parallel word-serial multiplier; cryptographic accelerator board; elliptic curve technique; finite field arithmetic module; finite field multiplier; Application specific integrated circuits; Arithmetic; Elliptic curve cryptography; Elliptic curves; Galois fields; NIST; Polynomials; Public key cryptography; Smart cards; Very large scale integration;
Conference_Titel :
IEEE-NEWCAS Conference, 2005. The 3rd International
Print_ISBN :
0-7803-8934-4
DOI :
10.1109/NEWCAS.2005.1496706
