Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Author

Liu, Q. ; Yagishita, A. ; Loubet, N. ; Khakifirooz, A. ; Kulkarni, P. ; Yamamoto, T. ; Cheng, K. ; Fujiwara, M. ; Cai, J. ; Dorman, D. ; Mehta, S. ; Khare, P. ; Yako, K. ; Zhu, Y. ; Mignot, S. ; Kanakasabapathy, S. ; Monfray, S. ; Boeuf, F. ; Koburger, C.

fYear

2010

Firstpage

61

Lastpage

62

Abstract

We present UTBB devices with a gate length (L_G) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V_bb) enables V_t modulation of more than 125mV with a V_bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V_t and power management applications. We explore the impact of GP, BOX thickness and V_bb on local V_t variability for the first time. Excellent A_Vt of 1.27 mV·μm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I_g) and lower external resistance (R_ext), thanks to a thicker inversion gate dielectric (T_inv) and body (T_si) thickness.

Keywords

CMOS integrated circuits; leakage currents; BOX fully depleted device integration; BOX thickness; UTBB devices; back bias; external resistance; gate leakage; gate-first high-k/metal; inversion gate dielectric; power management; raised source/drains; size 22 nm; size 25 nm; ultra-thin-body; Doping; International Electron Devices Meeting; Logic gates; Modulation; Performance evaluation; Resource description framework; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556120

Filename

5556120