Title :
High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths
Author :
Eneman, G. ; Yamaguchi, S. ; Ortolland, C. ; Takeoka, S. ; Witters, L. ; Chiarella, T. ; Favia, P. ; Hikavyy, A. ; Mitard, J. ; Kobayashi, M. ; Krom, R. ; Bender, H. ; Tseng, J. ; Wang, W.E. ; Vandervorst, W. ; Loo, R. ; Absil, P.P. ; Biesemans, S. ; Hoff
Author_Institution :
ESAT-INSYS, K.U Leuven, Leuven, Belgium
Abstract :
This paper is the first to provide a comprehensive study on the layout dependence of scaled Si1-xGex-channel pFETs. Drive current enhancement up to 90% is demonstrated for Si0.55Ge0.45-channel pFETs with LG = 35 nm and EOT = 0.9 nm when the transistor width (W) is scaled from 10 μm to 110 nm. This is attributed to a change in channel stress from biaxial compressive at large W to the more beneficial longitudinal uniaxial compressive stress at narrow W. These results are confirmed by both Nano-Beam Diffraction and TCAD analysis. Moreover, LG = 35 nm Si0.55Ge0.45 pFETs show 20% linear current enhancement for Length-Of-Diffusion (LOD) scaling below 200 nm. Both W- and LOD-scaling work favorably for Si1-xGex pFETs, as a consequence they are excellent candidates to be used in future HP CMOS technologies.
Keywords :
Ge-Si alloys; field effect transistors; nanoelectronics; HP CMOS technology; LOD scaling; Si0.55Ge0.45; TCAD analysis; biaxial compressive; channel stress; drive current enhancement; high-mobility channel PFET; layout dependence; length-of-diffusion; linear current enhancement; nano-beam diffraction; transistor width; Logic gates; Semiconductor device modeling; Silicon; Silicon germanium; Strain; Stress; Transistors;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556128
