Energy efficient modulation for a wireless network-on-chip architecture

As both power consumption and leakage currents will limit the scalability of future massively integrated computational systems, research into emerging technologies and devices to replace traditional metallic interconnects has become critical. In this paper we propose an initial implementation for a hybrid wireless network-on-chip (WiNoC) interconnect architecture, named iWISE, for current chip multiprocessors (CMPs). iWISE combines wired interconnects with wireless links that use both frequency and time division multiplexing to offer a balanced, flexible, orthogonal wireless data transfer among cores. We provide a basic description of the iWISE architecture and describe a practical solution for the implementation of wireless interconnects based on an on-off keying (OOK) modulator using ultra-compact Double Gate (DG) CMOS devices. The proposed OOK modulator takes advantage of DG-CMOS devices especially in building compact modulation and tunable amplification circuitry. Real applications from the benchmark suite PARSEC as well as synthetic traffic show an improvement in performance as well as a savings in power.