On the implementation of a multi-equalizer

Nowadays, the use of equalizers in wireless telecommunication systems is facilitated by the evolution of microelectronic. It is now possible to implement more than one equalizer in a programmable circuit. In (Dumais et al., 2004), a multi-equalizer (MEQ) architecture has been presented. The results have shown an improvement in BER performances when the propagation environment is fluctuating. This paper presents the FPGA implementation results of a DFE/LTE multi-equalizer. Multi-equalizing or parallel selection of multiple equalizers outputs is achieved by the definition of a cooperation strategy between filters, an algorithmic validation of the architecture by numerical simulations and a FPGA implementation of the structure.