Author :
Benner, S.J. ; Perez, G. ; Peters, D.W. ; Hue, K. ; O´Hagan, P.
Author_Institution :
Confluense, Allentown, PA, USA
Abstract :
Rotary chemical-mechanical polishing (CMP) tools are widely used for integrated circuit (IC) manufacture. Logic device manufacturing has required CMP for front end (FEOL) and back end (BEOL) processes, such as shallow trench isolation (STI), high-K metal gate (HKMG), dielectric (PMD, ILD, Contact), and interconnect metallization (Cu). Recently, manufacturers of memory ICs adopted Cu metallization which increased their CMP requirements. The normal mode of operation for a rotary CMP tool is one of dilution since fresh slurry is over-fed to a polishing pad that is saturated with spent slurry and process debris in an attempt to achieve pseudo-equilibrium for material removal rates. As a consequence, slurry consumption is significantly higher (by 2X or 3X) than that needed if the spent slurry and process debris were removed in-situ, resulting in a replenishment mode of operation. Changing the CMP tool´s mode of operation from dilution to replenishment has been demonstrated to significantly reduce slurry consumption while achieving higher material removal rates (MRR), in agreement with predictions. Rotary CMP tools recycle spent slurry and process debris under the wafer during the polish process. The maximum concentration of process debris occurs at end of polish when one is trying to achieve a high quality surface finish, which is precisely when debris will do the most damage. Much has been reported about the effect of long slurry residence times which result in kinetic decay of the process. However, virtually no data has been published on the impact of process debris residence time on wafer defects, due to the fact that until recently the ability to vary the debris residence time in a controlled manner was not available. Exhausting spent slurry and process by-products in-situ allows removing debris that can cause wafer defects. Several attempts have been made to modify CMP tools and associated components (i.e., slurry delivery arm, pad, wafer retaining ring, etc.) to r- - educe slurry consumption; however, only one CMP tool modification provides control of both slurry and debris residence times, namely Pad Surface Manager (PSM). PSM, in its simplest mode of operation, can be described as a vacuum cleaner for the pad. Previously published data demonstrated 50% cost savings from reductions in slurry consumption, water consumption, and extended conditioning disk and pad life. This paper will present data that show the impact of PSM on CMP-induced wafer defects. CMP-induced scratches are typically caused by particles, such as agglomerated abrasive, pad debris, or materials of construction (i.e., plastic) larger than 1|im. A flare-up of microscratching can cause both yield loss and reliability issues, bringing a production line to a halt and resulting in premature failure of IC devices in the field. The forces exerted during CMP are more than sufficient to cause particle agglomeration in alumina- or silica-containing slurries. In-situ pad conditioning produces very large particles (e.g., 2 to 200μm) of polyurethane that has been identified as a source of chatter marks, scratches, and microscratches. Accusizer 780 particle size distribution data was acquired for commercially available slurry before and after oxide polishing with samples collected at 10 second intervals using PSM. The mean particle size shifted from 0.6μm to 1.6μm after 10 seconds of polishing and particles larger than 50μm were detected in the used slurry. The number of particles per ml larger than 1μm in the control sample of slurry was 0.13×10. After 10 seconds of polishing with in-situ pad conditioning, the number of particles per ml larger than 1^m increased to 5.7×104, more than a 40X increase. After 80 seconds of polishing, the number of particles per ml greater than 1fxm increased to >;33×104, a more than 250X increase over the control. As the number of particles per ml large
Keywords :
chemical mechanical polishing; integrated circuit manufacture; reliability; wafer level packaging; CMP tools; CMP-induced scratches; CMP-induced wafer defects; Cu metallization; alumina-containing slurries; back end process; energy dispersive spectroscopy; front end process; integrated circuit manufacture; logic device manufacturing; material removal rates; memory IC; pad conditioning; pad surface manager; process debris removal; rotary chemical-mechanical polishing; silica-containing slurries; slurry consumption; Abrasives; Atmospheric measurements; Effluents; Process control; Slurries; Surface treatment;