Title :
Wet etch step modelling to help shallow trench isolation module control
Author :
Roussy, A. ; Gedion, M. ; Crousier, N. ; Pinaton, J. ; Labory, K.
Author_Institution :
EMSE-CMP Georges Charpak, Gardanne, France
Abstract :
We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example the lot to lot variability (a lot equals 25 wafers). The developed predictive model is based on a Design Of Experiments (DOE).
Keywords :
CMOS integrated circuits; design of experiments; etching; isolation technology; CMOS technology; design of experiments; shallow trench isolation module control; wet etch step modelling; CMOS integrated circuits; Predictive models; Process control; Semiconductor device modeling; Wet etching; Design of Experiments; Run to Run; Shallow Trench Isolation; Wet Etch process;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI
Conference_Location :
Saratoga Springs, NY
Print_ISBN :
978-1-61284-408-4
DOI :
10.1109/ASMC.2011.5898188
