Advanced floating gate CD uniformity control in the 75nm node NOR flash memory

This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger as the cell transistor size becomes smaller. The etch chamber effect is minimized by developing CF₄/CHF₃/N₂ plasma at 15mTorr pressure that provides better ECD uniformity within wafer.