Thermal budget reduction and throughput enhancement for CMOS Epi stressors via wet clean interface contamination evaluation and control

In this paper we present characterization, analysis, and methodology for the reduction of surface impurities trapped in the silicon layers at the onset of epitaxial growth. In CVD silicon technology, wet and dry clean of the silicon surface are used to remove native oxide from the surface. However, there are still residual impurities that require desorption via thermal baking to provide a clean interface. This thermal baking leads to unwanted increase of thermal budget. The greater the surface impurities concentration the longer and higher temperature is required for removal of these impurities. In production line environment, long queue times (up to 24 hours) are possible. During these queue times, impurities rebuild up on the surface after the initial wet clean. The combination of ultra-high purity gases and low-pressures during thermal bakes can be used to minimize thermal bake temperatures.