Decoded ultra-high definition video display system

Author

Weihua Qiu ; Yonglin Xue

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol.(TNList), Beijing, China

fYear

2015

Firstpage

294

Lastpage

295

Abstract

With the evolution from high definition (HD) to ultra-high definition (UHD), we face great challenges of increasing data rate and computational complexity. The solutions to real-time video transmission and display attract much research interest. In this paper, a hardware architecture based on field-programmable gate array (FPGA) is proposed for decoded UHD video display system. In the architecture, efficient memory management and parallel processing are applied to reduce operational frequency and achieve better real-time performance. The design has been successfully implemented on Altera FPGA, whereby 4K UHD video can be displayed on one single 4K screen smoothly.

Keywords

field programmable gate arrays; high definition video; parallel processing; storage management; video coding; FPGA; decoded ultra-high definition video display system; field-programmable gate array; hardware architecture; memory management; parallel processing; real-time video transmission; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Image color analysis; Real-time systems; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics - Taiwan (ICCE-TW), 2015 IEEE International Conference on

Conference_Location

Taipei

Type

conf

DOI

10.1109/ICCE-TW.2015.7216906

Filename

7216906