Title :
Increase fab capacity: With predictive short-interval scheduling
Author_Institution :
Appl. Mater.® AGS, Salt Lake City, UT, USA
Abstract :
The lithography cell is widely accepted as the most challenging area of a fab to manage cost effectively. Reticle coordination, re-entrant flows and frequent set-up changes create bottlenecks in the Litho module. There is a strong need to use optimization to better match lots and tools, keeping litho tools fully utilized and reducing wafer cycle time. A new solution, called Applied SmartSched™, for the first time integrates Real-Time Dispatching (APF RTD®) policies with locally optimized short-interval schedules to increase fab throughput and optimize litho tool utilization by converting `white space´ to available capacity. It produces a schedule whose output is executed by the RTD. Its predictive techniques determine precisely where work-in-process (WIP) and reticles will be to efficiently process the WIP. This novel technology is now being deployed in lithography modules of production fabs; initial results show over 2% increase in litho wafers out and litho tool utilization improvements greater than 1%. This advanced scheduling system looks upstream and downstream to see WIP status in order to better plan and schedule work in the litho area. SmartSched groups WIP better, increasing available capacity resulting in higher throughput. It has demonstrated a throughput improvement of 2.1% in a production litho module. Additionally the software is achieving a>;1% improvement in litho tool utilization. The SmartSched technology uses 3 major components that share the work to better pick the best lot to process. (1) Real-time data generation (2) Simulation-based prediction (3) Optimized short-interval scheduling This advanced scheduling approach is providing manufacturers with dramatically improved results, in critical photolithography areas.
Keywords :
photolithography; reticles; scheduling; semiconductor device manufacture; work in progress; Applied SmartSched™; WIP; fab capacity; fab throughput; litho tool utilization; litho wafers; lithography cell; lithography modules; optimized short interval scheduling; photolithography; predictive short interval scheduling; real-time data generation; real-time dispatching policies; reticles; simulation based prediction; work-in-process; Dispatching; Engines; Job shop scheduling; Lithography; Optimal scheduling; Schedules;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI
Conference_Location :
Saratoga Springs, NY
Print_ISBN :
978-1-61284-408-4
Electronic_ISBN :
1078-8743
DOI :
10.1109/ASMC.2011.5898205