Title :
Methodology for Cycle-Accurate DRAM Performance Analysis
Author :
Ikodinovic, Igor
Author_Institution :
Dept. of Multimedia Archit. & Performance, Qualcomm, Markham, ON, Canada
Abstract :
A new methodology for DRAM performance analysis has been proposed based on accurate characterization of DRAM bus cycles. The proposed methodology allows cycle-accurate performance analysis of arbitrary DRAM traces, obviates the need for functional simulations, allows accurate estimation of DRAM performance maximum, and enables root causing of suboptimal DRAM operation.
Keywords :
DRAM chips; DRAM bus cycles; arbitrary DRAM traces; cycle-accurate DRAM performance analysis; functional simulation; suboptimal DRAM operation; Analytical models; Computational modeling; Performance analysis; Performance evaluation; Protocols; Random access memory; Timing; DRAM; formal models; modeling methodologies; performance analysis and design aids;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2014.2346184
