Title :
A 30V EDMOS with Orthogonal Gate Structure Based on a 0.1μm CMOS Technology
Author :
Wang, Hao ; Xu, H. P Edward ; Ng, Wai Tung ; Fukumoto, Kenji ; Abe, Ken ; Ishikawa, Akira ; Imai, Hisaya ; Sakai, Kimio ; Takasuka, Kaoru
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Toronto, Toronto, ON
Abstract :
A transistor with an orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has a horizontal section to provide normal gate control and a vertical section to provide field shaping. This device is implemented in a 0.18 mum 30 V HV-CMOS process. Comparing to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The Figure-of-Merit (FOM) is improved by 37.5%.
Keywords :
CMOS integrated circuits; logic gates; EDMOS; HV-CMOS process; field shaping; figure-of-merit; gate-to-drain overlap capacitance; normal gate control; orthogonal gate electrode; orthogonal gate structure; CMOS process; CMOS technology; Capacitance; Electrodes; Fabrication; MOSFETs; Power semiconductor devices; Shape control; Switching loss; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-1532-8
Electronic_ISBN :
978-1-4244-1533-5
DOI :
10.1109/ISPSD.2008.4538887
