DocumentCode
172606
Title
Integration of a multi-layer Inter-Gate Dielectric with hybrid floating gate towards 10nm planar NAND flash
Author
Breuil, L. ; Blomme, P. ; Tan, C.-L. ; Lisoni, J.G. ; Souriau, L. ; Zahid, M.B. ; Richard, O. ; Bender, Hugo ; Van den bosch, G. ; Van Houdt, J.
fYear
2014
fDate
18-21 May 2014
Firstpage
1
Lastpage
4
Abstract
We demonstrate the integration of multi-layer Inter-Gate Dielectrics (IGD) together with a thin Hybrid Floating Gate (HFG), in aggressively scaled planar NAND cells. The results show that excellent memory performance is obtained in short gate length transistors, with good retention and endurance. Simulations indicate that such gate stacks can drive the planar NAND Flash scaling down to 10 nm node.
Keywords
NAND circuits; dielectric materials; flash memories; aggressively scaled planar NAND cells; gate stacks; hybrid floating gate; memory performance; multilayer inter-gate dielectric; planar NAND flash; short gate length transistors; size 10 nm; Aluminum oxide; Couplings; Dielectrics; Flash memories; Logic gates; Nonvolatile memory; Tin; High-k dielectric; Hybrid Floating Gate; Inter-Gate Dielectric; NAND Flash;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2014 IEEE 6th International
Conference_Location
Taipei
Print_ISBN
978-1-4799-3594-9
Type
conf
DOI
10.1109/IMW.2014.6849363
Filename
6849363
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