Title :
A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance
Author :
Yong Kyu Lee ; Boyoung Seo ; Tea-Kwang Yu ; Bongsang Lee ; Euiyeol Kim ; Changmin Jeon ; Weonho Park ; Yongtae Kim ; Duckhyung Lee ; Hyosang Lee ; Sunghee Cho
Author_Institution :
Syst. LSI Div., Samsung Electron. Co., Yongin, South Korea
Abstract :
For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triple-gate flash architecture, high speed operation (write time of 25us and erase operation of less than 2ms) and robust reliability (1M cycle, 150 □ retention) are achieved.
Keywords :
circuit optimisation; flash memories; logic circuits; 1M cycling endurance; IPs; logic compatibility; logic compatible-split-gate embedded flash memory; logic device characteristics; process integration; process optimization; robust reliability; shift minimization; size 45 nm; storage capacity 4 Mbit; time 25 mus; triple-gate flash architecture; Automotive engineering; IP networks; Logic gates; Optimization; Reliability; Split gate flash memory cells; Transistors;
Conference_Titel :
Memory Workshop (IMW), 2014 IEEE 6th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4799-3594-9
DOI :
10.1109/IMW.2014.6849369