A 90nm 32-mb phase change memory with flash SPI compatibility

A 32-Mb Phase Change Memory is realized in a 90nm 6-Metal process. An erase speed of 10.0-Mb/second and program speed of 35.6-Mb/second is achieved. The cell retention is interpolated to be 10 years at 85°C and cell endurance is measured to be 10⁹ cycles. The 25F² mushroom cell phase change memory utilizes a planar transistor. An ECC solution is employed to correct two bits out of a 128-bit data bus, with a 12% chip area overhead. The part is compliant with an SPI spec used for a NOR flash part. Word and bit redundancy are used for repairing defective bits. Fuse information is stored in PCM elements using a technique that increases the reliability of the fuse information, enabling it to withstand a solder cycle. A method is used to ensure proper fuse download at power up, even with the asynchronous power on behavior. Power islands are developed to disable both the high voltage supply needed for writes and peripheral logic needed for the datapath when in a standby mode, thereby reducing standby current.