Title :
Novel read disturb failure mechanism induced by FLASH cycling
Author :
Brand, Adam ; Wu, Ken ; Pan, Sam ; Chin, David
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The read disturb failure mechanism reported causes unselected erased bits residing on selected wordlines to gain charge under low field conditions, causing them to appear programmed. This failure appears to be due to electron tunneling barrier lowering by positive charge trapped during program/erase cycling. The Si-SiO/sub 2/ barrier in failing bits is reduced from 3.0 eV to under 1.0 eV at 70 degrees C. The FLASH EPROM array failure rate dependence on cycling, stress voltage, temperature, and duty cycle is characterized. A low failure rate has been found for the fabrication process studied.<>
Keywords :
EPROM; circuit reliability; failure analysis; integrated circuit testing; tunnelling; 70 degC; FLASH EPROM array; FLASH cycling; Si-SiO/sub 2/ barrier; electron tunneling barrier lowering; failure rate dependence; positive charge; product reliability; program/erase cycling; read disturb failure mechanism; EPROM; Educational institutions; Electron traps; Fabrication; Failure analysis; Stress; Temperature dependence; Testing; Tunneling; Voltage;
Conference_Titel :
Reliability Physics Symposium, 1993. 31st Annual Proceedings., International
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
0-7803-0782-8
DOI :
10.1109/RELPHY.1993.283291
