Byte alterable embedded EEPROM with B4-HE architecture achieving 10usec programming and 57F2 cell size

Author

Shukuri, S. ; Ajika, N. ; Shimizu, Shogo ; Otoi, H. ; Mihara, Mitsuharu ; Kawajiri, Y. ; Ogura, Tsuneo ; Kobayashi, Kaoru ; Nakashima, Masahiro

Author_Institution

GENUSION Inc., Amagasaki, Japan

fYear

2014

fDate

18-21 May 2014

Firstpage

1

Lastpage

3

Abstract

This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90 nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10 us and erase time of 1 ms. It is demonstrated that the excellent capability of more than 10 years data retention at 150 C. In addition, a fully designed 90 nm B4-EEPROM macro specification has been investigated, and the unit cell size can be designed 57F2, which is a half those of conventional EEPROM cell size of 80-100F2.

Keywords

CMOS digital integrated circuits; EPROM; hot carriers; logic gates; tunnelling; AND-type unit cell; B4-EEPROM cell array; B4-EEPROM macro specification; B4-HE architecture; back-bias assisted band-to-band tunneling hot-electron injection; byte alterable EEPROM; disturb-free operation; erasure cycling; flash process; single-pulse program; size 90 nm; time 1 ms; time 10 mus; Arrays; EPROM; Logic gates; Microprocessors; Programming; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2014 IEEE 6th International

Conference_Location

Taipei

Print_ISBN

978-1-4799-3594-9

Type

conf

DOI

10.1109/IMW.2014.6849386

Filename

6849386