Title :
System in wafer-level package technology with RDL-first process
Author :
Motohashi, Norikazu ; Kimura, Takehiro ; Mineo, Kazuyuki ; Yamada, Yusuke ; Nishiyama, Tomohiro ; Shibuya, Koujiro ; Kobayashi, Hiroaki ; Kurita, Yoichiro ; Kawano, Masaya
Author_Institution :
Renesas Electron. Corp., Sagamihara, Japan
Abstract :
We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.
Keywords :
reflow soldering; wafer bonding; wafer level packaging; RDL-first process; chip-I/O density; design flexibility; die-to-wafer bonding; fan-out wafer-level-packages; fine-pitch reflow soldering; high-throughput fabrication; package miniaturization; system-in-wafer-level package; Bonding; Copper; Nickel; Prototypes; Resins; Wiring;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2011.5898492
