Title :
Performance and reliability of NAND flash/SCM hybrid SSD during write/erase cycling
Author :
Tanakamaru, Shuhei ; Hosaka, Sumio ; Johguchi, Koh ; Takeuchi, Ken
Author_Institution :
Chuo Univ., Tokyo, Japan
Abstract :
This paper describes the comprehensive analysis on the performance of NAND flash/storage-class memory (SCM) hybrid solid-state drive (SSD) during write/erase (W/E) cycling for various applications. Since bit-error rate (BER) increases by cycling, increasingly stronger ECC should be applied, which results in longer ECC calculation time. Both program/erase latencies of the NAND flash memory and ECC calculation time change during W/E cycling and have complex effects on the SSD performance. By assuming that the reliability of SCM simultaneously degrades with NAND, the SSD performance is also evaluated by the transaction-level simulator. Three key results are derived: (i) the error-correction latency strongly impacts both NAND-only and hybrid SSD´s performance, (ii) the SSD performance with error-correction is sensitive to the workload and (iii) reliability requirements of NAND and SCM are defined for various applications. The BER of SCM can be 1% at maximum.
Keywords :
NAND circuits; error correction codes; flash memories; integrated circuit reliability; BER; ECC; NAND flash memory-SCM hybrid SSD; SCM reliability; W-E cycling; bit-error rate; error-correcting code; error-correction latency; hybrid solid-state drive; program-erase latency; storage-class memory; transaction-level simulator; write-erase cycling; Bit error rate; Decoding; Encoding; Error correction codes; Flash memories; Reliability; Throughput; NAND flash memory; error-correcting code; reliability; solid-state drive (SSD); storage-class memory;
Conference_Titel :
Memory Workshop (IMW), 2014 IEEE 6th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4799-3594-9
DOI :
10.1109/IMW.2014.6849389