Characterization of 64kb test chip for touch application on 90nm SONOS technology

Author

Kwon Young-Jun ; Lee Tae-Ho ; Kim Jae-Gwan ; Park Sung-Kun ; Cho In-Wook ; Yoo Kyung-Dong ; Joo Young-Dong ; Kim Seung-Deok ; Lee Jun-Ho ; Choi Chul-Hoon

Author_Institution

Syst. IC Div., SK HYNIX Inc., Cheongju, South Korea

fYear

2014

fDate

18-21 May 2014

Firstpage

1

Lastpage

4

Abstract

In this paper, an embedded 2T SONOS nonvolatile memory structure has been proposed for an embedded NVM cell in 90nm standard HVCMOS process. This nonvolatile cell can be fabricated by several steps such as ONO formation, cell junction implant, removal ONO films, those steps are non-critical processes and masks. The cell is operated by CHEI programming and BTBT-HHI erasing. The cell has been confirmed with 64kB test chip, program and erase operation, cycling, data retention. With wide window and good reliability, the cell is good for medium density embedded memory.

Keywords

CMOS memory circuits; embedded systems; logic testing; random-access storage; BTBT-HHI erasing; CHEI programming; ONO formation; cell junction implant; data retention; embedded 2T SONOS nonvolatile memory structure; embedded NVM cell; erase operation; medium density embedded memory; noncritical processes; nonvolatile cell; program operation; removal ONO films; size 90 nm; standard HVCMOS process; storage capacity 64 Kbit; test chip; touch application; Arrays; Junctions; Logic gates; Nonvolatile memory; Reliability; SONOS devices; Transistors; BTBT-HHI; CHEI; EEPROM; Flash; NVM; SONOS; cycling; data retention; embedded; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2014 IEEE 6th International

Conference_Location

Taipei

Print_ISBN

978-1-4799-3594-9

Type

conf

DOI

10.1109/IMW.2014.6849390

Filename

6849390